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B2PCOE Pb-Free Manhattan Project Report Phase I - Reliability

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The complete PDF version of the Lead-Free Electronics Manhattan Project - Phase I publication can be downloaded here. (~5 MB)

Contents

7.1 Introduction

The introduction of Pb-free materials and processes (LFM&P) into A&D electronics systems and products will significantly affect the ability to predict and verify reliability. The causes of this include:

  • Incompletely characterized materials.
  • Wider and changing suite of materials.
  • Immature processes with narrower process windows.
  • Intrinsic complexities of the physical properties and metallurgy of Pb-free solders.

These factors currently confound the ability to model and interpret test results, and therefore limit the confidence in the methods used to predict reliability.

7.1.1 Reliability Program Activities

Reliability programs are required to ensure that systems perform their intended function over their intended lifetime and in their intended usage environment. Nearly all A&D programs specify reliability requirements that include metrics germane to the particular system application, and under specific service life cycle conditions. Top-level system reliability and associated environmental requirements are converted into a set of derived requirements for subsystems. It is not anticipated that the standard methodologies currently employed in this flow down process will require modification as a result of the introduction of Pb-free materials and processes.

It is standard practice for A&D programs to have a formal reliability program in place to ensure that appropriate activities occur in all lifecycle phases, and to establish that the overall reliability requirements are satisfied. The flow of reliability interaction with the product life cycle is depicted in Figure 7.1.

Figure 7.1 Basic elements of a reliability program. The color coding reflects the expected relative impact of LFM&P on each portion of the reliability program.

The form and structure of reliability programs are not expected to change. It is a common requirement that various forms of reliability predictions be performed for A&D systems. System level reliability predictions are typically performed in accordance with standards such as MIL-HDBK-217, which is not recommended as a best practice in IEEE-1413.1, and has not been updated in over a decade. This document is completely out of step with the majority of electronic devices being fielded today, and does not consider LFM&P at all.

Recently introduced GEIA-STD-0009 requires an understanding of failure sources in predicting system level reliability. The LEAP-WG is preparing a document (GEIA-HDBK-0005-4) that is intended to provide guidance for the performance of reliability assessments of A&D systems incorporating LFM&P. It is recommended that these documents serve as a basis for the implementation of improved practices, and that the team working on this document continue to be supported to perform future updates and refinements.

Once a system has moved past design into manufacturing and integration, new reliability tasks of verification tracking begins to take place. The overall structure of these program elements is not anticipated to require modification to accommodate the needs of LFM&P. Specific test conditions employed for qualification and screening may not necessarily change, but the interpretation of test results need to be re-examined. Material testing based on LFM&P must be supported to inform these interpretations. Ultimately, reliability must focus on the impact of LFM&P on failure mechanisms and dominant sources of failure, which are discussed in this section.

Tracking and reporting of failures should be able to proceed as with SnPb product. Enhanced tracking of pilot runs of Pb-free products will be required, however, to maximize the value of these tests.

7.1.2 Failure Modes and Mechanisms

It is necessary to have an understanding of the applicable failure modes and mechanisms, as well as models, in order to make meaningful predictions and to perform meaningful tests. The remainder of this section provides detailed information on each of the principal hardware failure mechanisms affecting soldered A&D assemblies.

Reliability failures are divided into early (infant), random (in use), and wearout (end-of-life) classes. The total failure rate as a function of time is represented by the sum of these three subsets. This notion is typically exemplified by the so-called "bathtub curve," which is illustrated in the following figure.

Figure 7.2 Bathtub curve illustrating how the three classes of failure modes affect system level reliability over the entire lifecycle.

Early failures are the result of manufacturing or material defects. The principal tools used to control these failures are inspection and screening tests. Improper control of these failures results in the left hand side of the bathtub curve moving out to the right, thereby affecting the failure rate of the product in the field during the first portion of its life. This excess unreliability persists until such time that the affected population falls out through failure or removal.

Wearout failures are also often referred to as "end-of-life" failures. The principal tools used to control these failures are life testing and associated modeling. Improper control of this class of failures results in the right-hand side of the bathtub curve shifting leftward. The result of this is that the unreliability of the system increases prematurely and it may become unusable before completing the required service life.

Random or in-use failures result from defects escaping design and manufacture, early wearout failures, as well as unanticipated changes in use conditions. The in-use failure rate is often represented as being constant over time, which manifests itself as a steady-state mean time between failure (MTBF) over the service life of the system. Random failure modes are controlled through a variety of processes, with a robust failure reporting and corrective action (FRACA) process being chief among them.

Each of the specific failure sources discussed in detail below is summarized in the following table. It is intended to provide a snapshot of the impact of LFM&P on the most important failure sources, and the adequacy of the Current Baseline Practices employed to manage these failure sources. Also within the table, each failure is assigned to one of the three portions of the bathtub curve so as to illustrate the potential impact on system level reliability.

Site Failure Source Mode Stage Primary Driver Management Impact of Lead Free Repair/ Rework Impact Risk with Current Best Practice
Solder Joint Manufacturing Defects Shorts/ Opens Early Mechanical Loads Inspection/ Screen Medium High Medium
Solder Joint Thermal Cycle Fatigue Opens End-of-Life Temperature Test/Model Medium Medium Medium/ High
Solder Joint High Cycle Vibration Fatigue Opens End-of-Life Vibration Test/Model Medium Medium Medium
Solder Joint Shock/Low Cycle Vibration Fatigue Opens End-of-Life Shock/ Vibration Test/Model High High Medium
Solder Joint Combined Environments Shorts/ Opens End-of-Life Temperature/ Vibration Test/Model High High High
Solder Joint Mixed Solders Shorts/ Opens Random Temperature/ Vibration Test/Model High High High
Solder Joint Underfill Opens End-of-Life Temperature Test/Model Medium Medium Medium
Solder Joint Low Temperature Brittle Fracture Opens End-of-Life Shock/ Vibration Test Medium Medium Medium
Solder Joint Creep Rupture Opens End-of-Life Temperature/ Mechanical Load Test/Model High Medium High
Solder Joint Electromigration Opens End-of-Life Current Density Test/Model Medium Medium Medium
Solder Joint Tin Pest Opens Random Temperature Test Medium Low Low
PWB Manufacturing Defects Shorts/ Opens Early Temperature/ Vibration/ Humidity Inspection/ Screen High High Medium
PWB Barrel Cracks Opens End-of-Life Temperature Test/Model Medium High Low
PWB Trace Fatigue Cracks Opens End-of-Life Temperature/ Vibration/ Shock Test/Model Medium High Low
PWB Pad Cratering Opens Early/ End-of-Life Temperature/ Vibration/ Shock Test High High Medium
PWB Conductive Anodic Filament Shorts Early Voltage/ Humidity Test/Model High High Medium
PWB Creep Corrosion and Dendritic Growth Shorts Random/ End-of-Life Corrosive Atmospheres Test Medium Medium Medium
Assembly Tin Whiskers Shorts Random Varied Test/Model High Low Medium
Components Temperature Sensitivity Shorts/ Opens Early Temperature Inspection/ Screen High High Medium
Components BGA CTE and Warpage Opens Early Temperature/ Vibration Inspection/ Screen Medium High Medium
Components Plastic Component Delamination Opens Early Humidity/ Temperature/ Vibration Inspection/ Screen Medium Medium Low

Table 7.1 Failure sources and their relationship to the reliability of Pb-free A&D systems.

7.1.3 Rework and Repair Effects

Rework and repair activities play a significant role in the manufacture and sustainment of A&D systems. LFM&P will have a significant impact on rework and repair activities which are expected to impact reliability. From this perspective, a more disciplined approach and deeper understanding of rework/repair will be needed. The severity of the interaction between failure sources and rework/repair is highlighted in Table 7.1 above.

7.2 Failure Sources

7.2.1 Solder Interconnections

Solder interconnects are required to provide electrical and mechanical connections between packaged devices and large connection structures, most commonly, the printed wiring board. One of the most obvious impacts to A&D products due to supply chain adoption of RoHS materials is the change from a SnPb solder to a Pb-free solder. While a wide variety of Pb-free solders exist and more are being developed, tin-silver-copper (SAC) and tin-copper solder have been selected and are now widely used by the consumer and commercial industry. For tin-silver-copper solders, SAC305 and SAC405 have received the most significant amount of study with SAC305 taking the lead. For wave solder, the copper dissolution issue has been primarily responsible for SAC305 losing ground to tin-copper; usually in the form of tin-copper-nickel.

To date, a significant amount of research has been invested in temperature cycling performance of Pb-free solders. Recently, attention has shifted to shock durability as consumer adopters found issues with drop shock reliability in hand-held applications. Acceleration and time to failure models based on material science and SnPb solder have been published, but their ability to predict field life has not be verified.

This section provides a discussion of the solder interconnect failure sources. It is divided into loading conditions which occur during the life and testing of the solder joint, with special consideration to interconnects formed by combining solders of differing composition, which occurs with attachment of ball grid array packages.

Manufacturing Defects

Improper manufacturing processes can result in improperly formed or damaged solder interconnects. These compromised solder interconnects can lead to both early and elevated random failures. The identification and sources of defects in SnPb solder interconnects are well documented and controlled by the design and manufacturing processes. LFM&P introduces an elevated risk for defects that can only be resolved by cooperation between reliability, manufacturing, and design. Current Pb-free solders require higher assembly temperatures of 20 °C or more compared to those used for SnPb solder assembly. This results in higher rates for intermetallic formation and greater deformations, which when uncontrolled, will result in increased levels of defects. Many of these defects have been identified by advanced product development teams and it is critical that manufacturing develop and qualify practices to control them. Some defects can be identified by inspection processes while others may have to be removed by stress screens.

  • Current Baseline Practice
    • Non-destructive inspection is used to identify gross defects such as poorly formed joints, starved joints, tombstoning, and high contact angles. Area array technology requires X-ray inspection for voiding, missing solder connections, starved joints, and bridging. Current inspection protocols are identified in industry standards such as IPC-610D and IPC-7095. In addition, destructive analysis of assembly samples may be used to verify proper joint formation. Environmental stress screens are commonly used to precipitate failure of defective solder interconnects. All of these procedures are impacted by conversion to Pb-free solder.
  • Issues/Gaps/Misconceptions
    • Surface inspections are not sufficient to identify all interconnect defects. Due to material composition, the surface appearance of SAC solders may be grainy and shrink cracks may occur. For SAC ball grid arrays assembled with SnPb solder, the solder surface appearance and X-ray inspection are insufficient to determine joint reliability.
    • ESS reduces the life of a solder interconnect, requiring balance between capturing defective solder interconnects versus reducing the life of properly formed solder joints. In development, it is important to verify that a sufficient life margin remains after ESS (see Combined Loading later in this section).
  • Conclusions and Recommendations
    • It is critical that the assembly manufacturers develop qualified processes that eliminate or control defect levels. Mixed solder cannot be discerned by the normal inspection processes. Therefore, solder composition of BGA spheres must be tightly controlled.

Interconnect Fatigue

Solder interconnects may fail by wear out (fatigue) under high cycle (vibration) or low cycle (thermal cycling, repetitive shock) conditions, or due to a single overstress event (shock). The microstructure and damage evolution in mainstream Pb-free solders differ significantly from SnPb solders. Thus, for example, effects of Sn grain orientation lead to significant scatter in fatigue resistance, strength, and creep properties [1-4], so that the most stressed (corner) joint is not necessarily the first that fails. Additionally, there tends to be more incidences of early failures. Models and rules of thumb for evaluating life expectancy of interconnects, under anticipated life cycle loads which worked for SnPb, may not be appropriate for mainstream lead free solders. As a further complication, LFM&P can weaken laminate interfaces, resulting in pad cratering.

Temperature Cycling

Temperature excursions arising from operation and environmental conditions are known to limit the life of CCAs and need to be assessed based on the design requirement. Temperature cycling has been one of the most intensely studied topics related to LFM&P. For relatively small temperature excursions in the range of 0 to 100 °C with low to moderate ramp rates and short dwell times, the performance of SAC305/405 has been shown to be far superior to SnPb. For a wider range, such as -55 to 125 °C and longer dwell times, the fatigue life of SAC305/405 is further reduced and may end up slightly shorter than for SnPb, depending on package type. Fatigue life models have been derived and a significant set of test data generated over the past ten years.

  • Current Baseline Practice
    • The life expectancy of solder interconnects under use conditions is assessed in design through models and/or validated through qualification tests. The latter requires acceleration factors or rules of thumb to determine the level of testing required to verify that wearout failures will not occur in use. An acceleration factor (AF) is defined as AF = Nuse / Ntest where Nuse is the time or cycles to failure in use and Ntest is the time or cycles to failure in test. For SnPb, industry standards such as IPC-9701, reference the so-called "Engelmaier Model" [5-7]. In addition, a number of temperature cycle fatigue failure modeling approaches have been developed and documented in the literature [8-20]. Many of these approaches require detailed finite element modeling, but the "Engelmaier Model" [9, 14, 15], the SRS model [11], and the Norris Landzberg model [8, 17, 18] – originally developed by IBM for C4 technology – do not. The latter is, in fact, not a true fatigue life model but only predicts acceleration factors. In general, the fatigue models are based on the Manson-Coffin or Morrow models, which relate the number of cycles to failure, Nf, to cyclic strain range, Δγ, or cyclic strain energy, ΔW. Some of the prevalent models are identified in Table 7.2.
Model Model Form Requires FEA Model Constants Available for SnPb Model Constants Available for Pb-Free (SAC305)
IPC-9701 (Engelmaier [9,13,14]) Nf = 1/2 (Δγ/2εf)1/c No Yes Yes
SRS (Clech [11]) N = C1(ΔW)d1 No Yes Yes
Norris Landzberg [8,17-19] AF = (ff/ft)-m(ΔTt/ΔTf)-n exp (Ea/K)[(1/Tf)-(1/Tt)] No Yes Yes
Inelastic Energy (Schubert [16]) N = C2(ΔW)d2 Yes Yes Yes
Energy Partitioning (Dasgupta [10]) Energy = Ue + Wp + Wcr = UoNfeb' + WpoNfpc' + WcoNfcd' Yes Yes Yes
Strain Energy (Syed [12]) Nf = (0.02EGBS + 0.063EMC) Yes Yes Yes

Table 7.2 Temperature Cycle Fatigue Models

  • Issues/Gaps/Misconceptions
    • Existing SnPb solder reliability models suffer from a variety of issues but have been accepted due to the long use of SnPb solders. Clearly our predictive experience with Pb-free solder interconnect reliability, lacks the maturity of the knowledge ascertained over the years with predicting SnPb interconnect reliability.
    • For Pb-free solders, the influence of process parameters, solder volume, long term aging, mixed alloys and load history are not adequately addressed or are simply ignored by existing models. These omissions raise serious concerns over the ability of existing models to predict long-term life performance.
    • For instance, many BGA packages are available with solder balls of low-silver and quaternary alloys that may improve drop shock behavior. However, these alloys may have significantly negative influences on temperature cycling performance, and currently, we cannot directly account for these mixed alloys in fatigue life between test and field.
    • Limited isothermal aging led to clear reductions in the thermal cycling fatigue life of large SAC305 joints [23, 24]. Smaller joints, lower silver content, and longer aging are all expected to show a greater sensitivity, but this has yet to be quantified. Overall, micro-structural aging is not understood well enough and short term high temperature aging (1000 hours @125 °C) does not necessarily represent a worst case simulation of effects which may occur after even a few years of operation (Appendix).
    • Linear damage accumulation is invariably assumed when predicting the performance of Pb-free solder interconnects subject to the non-uniform temperature excursions commonly experienced by fielded electronics. However, this has yet to be justified (see Combined Loading).
    • Material properties of mainstream Pb-free solders, such as creep, have been demonstrated to change dramatically over time.
    • Finally, even relative comparisons (ranking) of assembly life may depend on the dwell time used in accelerated testing (Appendix). This result suggests significant consequences for design, materials, and process optimization.
  • Conclusions and Recommendations
    • Reliability programs should be advised that the level of maturity for fatigue life estimation of mainstream Pb-free materials is not at the level of SnPb solder. In addition, the combined effects of aging, alloy mixing, and variations in environmental profile may lead to significant errors in model predicted life expectancy. These combined effects may result in acceleration factor errors of five to ten times or more, while further failure mechanisms may be different depending on service conditions (Appendix).
    • It is recommended to place Pb-free assemblies in the field under a variety of environments and non-critical applications as soon as possible. This is the only means of generating the field experience that will be necessary to validate models.
    • Research into aging effects, failure mechanisms, mixed Pb-free alloys, and damage accumulation to improve existing or developing new models, should be supported.

Vibration (High Mechanical Cycle)

During their life cycle, A&D products are commonly subjected to a wide range of application-specific vibration. Vibration induced board curvature results in cyclic strains in the solder joints, but unlike temperature cycling, the loading is highly dependent upon component location and the numbers of cycles are characteristically an order of magnitude higher. SnPb solder interconnects were typically tested under severe load levels and issues arising from test were mitigated through the addition of stiffeners and bonding materials. For certain package types, mainstream Pb-free solders have demonstrated a lower durability than SnPb under elevated vibration levels. In addition, failures arising under high vibration levels are not limited to solder cracking but have included both trace failure and pad cratering. Figure 7.3 depicts a typical solder crack in a SAC joint, and Figure 7.4 reveals a vibration induced trace failure. Like SnPb, Pb-free solders will require mitigation to survive elevated vibration and shock loading. At present, insufficient testing has been conducted to validate simulation models and provide rules of thumb for when vibration mitigation must be applied.

Figure 7.3 Vibration induced solder fillet failure. Courtesy CALCE, UMD.
Figure 7.4 Vibration induced trace failure. Courtesy CALCE, UMD.
  • Current Baseline Practice
    • For applications with significant vibration life cycle loading, a designer will need to carefully consider part positioning and may need to intrinsically design for mitigation earlier than previously used with SnPb. Finite element models may be used to determine vibration induced board strain history. Additional finite element models may be used to determine vibration induced solder strain history. SAC305 model constants for the generalized Manson-Coffin model (Δε/2) = εf (Nf)c + σf/Ε (Nf)b have been published [25]. Vibration testing is most typically performed during product qualification using test methods described in MIL-STD-810. Test acceleration factors are often calculated using life assessment models or the Basquin relationship [26] NtStb = NuSub using an exponent which can range between four and nine. Qualification testing is not typically performed to failure.
  • Issues/Gaps/Misconceptions
    • Tests to failure of assemblies are expected to help identify reliability issues, but MIL-STD-810 and other tests do not require tests to failure. Passing a qualification is insufficient to determine life expectancy.
    • The modeling issues presented for the temperature cycling fatigue, as stated in previous sections, also apply for predicting vibration fatigue. The level of testing and data available for model development and validation for vibration fatigue is extremely limited. Isothermal aging of solder has been demonstrated to reduce vibration fatigue life of both SnPb and mainstream Pb-free solders. However, Pb-free solder exhibits a stronger aging dependence which makes it difficult to properly evaluate the effect during vibration testing.
    • The majority of reported vibration test data has either been from step stress tests showing SAC soldered interconnections failing prior to SnPb joints, or from time terminated tests with no failures for mainstream Pb-free solders. The latter results do not allow for the development of fatigue models, and the use of step stress tests requires the assumption of damage accumulation models unlikely to be even roughly valid (see Combined Loading).
    • A further challenge with vibration is that the failure of traces near the solder bond pads tend to confound model development, since fatigue constants and stress states are different for the traces, than for the solder. Elevating vibration stress levels in a step stress test can transition failure from a high cycle to low cycle fatigue involving crack growth in the interfacial intermetallics. Step stress test may thus suggest a higher acceleration of damage than will occur under normal field conditions.
  • Conclusions and Recommendations
    • Current vibration test practices in process and product validation may be sufficient to identify defects and prevent early failures. However, the lack of test to failure under single load levels, knowledge of mixed alloys, and micro-structural aging, does not allow confidence in model estimates.
    • Further research should be sponsored to establish vibration fatigue models based on package types and mainstream Pb-free solders used in CCA.

Shock Fracture and Low Mechanical Cycle

As loading rates increase, solder interconnect failure location tends to change from solder to intermetallic bond and trace fracture due to pad cratering. Limits and trends vary with design and materials, but shock fracture and low mechanical cycle failures tend to occur by cratering (see Pad Cratering in Section 7.2.4, Tin Pest) or at the interfaces. This is strongly exacerbated by the combination of harder Pb-free solders, weaker intermetallic structures, copper dissolution, poorly fabricated or unqualified board materials, and the sporadic occurrence of greatly defective intermetallic structures.

  • Current Baseline Practice
    • Shock and drop test standards are well established [27-31] and equally valid for Pb-free assemblies. There are currently no credible models or predictions for failures of interfacial intermetallic bonds or by cratering. At this time, the best current baseline practice is not to attempt to accelerate test conditions of shock and low cycle vibration, but rather to closely simulate actual service lifetime exposure during testing.
  • Issues/Gaps/Misconceptions
    • Existing predictive models do not account for factors such as mixed alloys, aging, or competing/combined failure mechanisms. As a result, little confidence can be placed in existing models for predicting failure under shock loading conditions.
    • Issues with an intermetallic bond can greatly affect shock performance. Unfortunately, these defects are sporadic and therefore are often missed due to sample size limitations. Sporadic defect mechanisms are also difficult to study and proposed remedies are hard to validate (proving a negative). Problems associated with various pad finishes are commonly declared solved because they "went away." The problem is surmised to have resulted from unspecified "process control problems" which are invariably claimed by suppliers, to be safely prevented for their products.
    • The gold embrittlement problem associated with excessive gold on Ni/Au pad finishes leading to a weak or less fatigue resistant intermetallic bond to the Ni, has received limited attention [32]. Rules of thumb for SnPb solder have not been examined sufficiently for main stream Pb-free solder alloys. Limited data suggests the problem is reduced for SAC solder [58]. In addition to gold embrittlement, new plating protocols and screening tests continue to be proposed and implemented to prevent black pad as phenomena also associated with Ni/Au pad finishes. Champagne voiding on immersion silver finishes appears preventable through new, published, industry practices [33]. Other defects are reported anecdotally and are often misinterpreted.
      • Sporadic Copper Nickel Tin Failure: Occasionally, a batch of BGAs with SAC balls will arrive with one to two balls missing from each. Otherwise, a batch will show brittle failure at Nickel pads on the component substrate soon after assembly to copper pads on the PCB. This problem has been traced to the quality of the plated Nickel on the component, but is not otherwise understood.
      • Copper Pad (Kirkendall) Voiding: The sporadic formation of voids near the interface between copper and the intermetallic bond continues to be underestimated across the industry. The problem is caused by the incorporation of impurities into the copper [59]. Pb-free solder with less ductility can exacerbate the problem. A quantitative understanding of the problematic mechanism, along with how the phenomena is accelerated, has generated some established practical remedies that still need to be implemented in a production environment [34].
      • Black Pad Fracture: This problem is unique to Electroless Nickel Immersion Gold (ENIG). The harder Pb-free solders strongly enhance the problem.
  • Conclusions and Recommendations
    • Shock and harsh mechanical cycling is most likely to cause a solder joint to fail by pad cratering or through the intermetallic bond to a pad. Either type of failure is dominated by defects, induced in processing or subsequent handling and service.
    • We recommend avoiding the use of Pb-free solder attachments in field mission-critical A&D hardware for applications that are subject to long-term aging, followed by significant shock levels. Shock resistance will depend upon the nature of the intermetallic interfaces, which will be affected by long-term aging in ways that we cannot predict now. If Pb-free solder attachments must be used, we recommended that accelerated aging be performed until the intermetallic thickness matches the thickness that is anticipated after worst-case service life, prior to performing conservative lifecycle shock testing.
    • We recommend a systematic research effort to fill the gaps identified above.

Combined Loading

Most A&D products are subjected to simultaneous and/or sequential combinations of loading while in use. As a result, tests that apply two or more concurrent loads in the hope of simulating actual field conditions are often used in product qualification. The most common combinations are the simultaneous application of temperature cycling and vibration, ESS, random vibration testing, and HALT testing. Sequences of different thermal excursions or mechanical loads, which are common in service, are usually not tested.

  • Current Baseline Practice
    • HALT testing is being performed on Pb-free product no differently than has been performed on SnPb products previously. HALT is intended to identify weaknesses rather than to be used for making life predictions.
    • Current practice for estimating life expectancy under combined loads is to apply a linear damage model that determines damage rate under individual loading conditions and sums up the damage. This can be expressed by: 1/Tl = 1/Tc + 1/Tv where: Tl= time to interconnect failure in that cycle, Tc = time to failure under thermal load, and Tv = time to failure under that vibration load.
  • Issues/Gaps/Misconceptions
    • Loading (damage) history can impact the damage rate under future loading conditions. Predictions based on current industry practice of linear damage superposition may there­fore be non-conservative. Attempts have been made to resolve this issue [35, 36], but a general industry consensus on a modeling approach has not even been established for SnPb. The ability to model combined loading conditions will also be strongly influenced by package formats that produce varying stress states within solder joints under combined loading conditions.
    • Recent work has shown an even more obvious breakdown of the linear damage assumption for sequential loading of lead free solder joints. Isothermal cycling (e.g., vibration) with a particular amplitude either reduced the life in subsequent cycling with a different amplitude by a factor of three more than predicted, or it extended subsequent life by a factor of two, depending on the combination of parameters. The potential consequences for any kind of cyclic loading are therefore significant.
  • Conclusions and Recommendations
    • ESS testing of Pb-free solder joints may easily be much more damaging than assumed, e.g., accelerated testing should be conducted after screening. Predictions of life under service conditions involving varying loads or thermal excursions, not to mention simultaneous loads, may be greatly misleading. There is an urgent need for systematic materials science-based research to establish a quantitative understanding of the accumulation of damage in Pb-free solders.
    • Until these issues are resolved, we cannot assign a level of confidence to quantitative predictions of life under service conditions involving strongly varying loads, but errors are potentially huge.
    • Given the current lack of understanding, we do not recommend the use of Pb-free solder attachments in mission critical A&D products when both vibration and thermal cycling contribute a significant amount of damage.

Mixed Solders

Mixing of Pb-free solder with SnPb or the mixing of two different Pb-free solders can result in solder joints that exhibit decreased reliability. Mixed alloy solder joints can pass all applicable inspections, yet may not provide a reasonable degree of reliability.

As part suppliers optimize their products for LFM&P, A&D manufacturers face a significant reduction in availability of parts with SnPb terminals. The majority of Pb-free parts with leads and leadless package formats do not pose a problem in terms of quantifying the reliability risk when assembled with SnPb solder. For Pb-free BGAs, however, assembly with SnPb solder presents a significant reliability risk [37]. The decision to combine Pb-free BGAs and a SnPb solder cannot be generally recommended, since results are highly dependent upon assembly and process. The issue of Pb-free BGAs in a SnPb solder process is covered in Section 4.0, Manufacturing. Other parts with lead (Pb) bearing terminals should not be used when changing over to LFM&P. Lead contamination has been shown to reduce Pb-free solder interconnect reliability in a highly variable fashion, and can introduce soldering defects that give rise to elevated infant mortality.

Potential mixing of disparate Pb-free solders could occur during repair activities. The effect of this on reliability is not understood and this practice should therefore be avoided. This requirement may create a significant burden during sustainment.

At present, inadequate data is available to predict the reliability for mixtures of Pb-free and SnPb solders. As such, the baseline practice should be to avoid mixing solders in assembly and rework and repair.

Underfill and Corner/Edge Bonding

Due to stated weaknesses under vibration, mechanical bending, and shock, designers may seek to improve robustness of solder interconnection through underfill and/or corner and edge staking. Such applications may restrict sustainment ability by eliminating or reducing the ability to repair/ rework the CCA.

  • Current Baseline Practice
    • The need for underfill and component staking may arise from prototype testing and design experience. When selecting and using underfills and compounds for component staking, it is critical to evaluate the impact of underfill through all anticipated life cycle loading conditions. For instance, it is known that underfills can shorten temperature cycle failure life of solder joints while extending vibration life times. Further, the application of underfills should be considered with respect to the assembly process and potential rework and repair operations. Rework/repair in areas adjacent underfilled parts may be also be inhibited.
  • Issues/Gaps/Misconceptions
    • The compatibility of underfills and staking materials with LFM&P needs to be understood. Poor adhesion with underfill or staking can create a larger problem.
    • Finite element modeling approaches for assessing life expectancy of underfilled and staked interconnect have been published. These published techniques have been demonstrated with one or more test conditions. However, the effectiveness of these modeling techniques for estimating life expectancy over long-term operation has not been satisfactorily documented. With regards to LFM&P, very little data is available.
  • Conclusions and Recommendations
    • Different materials are preferred for Pb-free than for SnPb. Flip chip underfilling is a very mature field, and most experiences apply to WL-CSPs. Other component underfilling is far from mature. Current repairable underfills may reduce Pb-free performance in thermal cycling – none of them improve it significantly. If repairability is required, consider corner/ edge bonding instead.
    • Service relevant conditions (strain rates, heating/cooling rates and maximum temperature) should be accounted for in accelerated testing if possible. Otherwise, independent materials testing should be employed to show that underfill creep can be ignored. Testing should emphasize long term degradation of underfill repairability with temperature and humidity (in the presence of realistic residues).
    • Non solder mask defined pads on PCB should be designed to prevent air bubble entrapment.

Low Temperature Brittle Fracture

In contrast with SnPb, SAC solders have exhibited a rapid transition from ductile to brittle fracture between -40 °C and -70 °C [38]. For A&D applications operating at extremely low temperatures, particularly under high stress and high strain loading conditions such as in mechanical shock, this may present a risk.

  • Current Baseline Practice
    • MIL-STD-810 requires testing at the minimum temperature if service extends into the brittle fracture regime, but this is not always rigorously followed.
  • Issues/Gaps/Misconceptions
    • Little information is available about SnPb solder behavior under shock and vibration at low temperatures, but many decades of successful field history in A&D products provides empirical assurance. No such assurance currently exists for Pb-free solders.
    • Existing models for shock do not adequately consider impact of the low temperature transition on solder properties. Current test practices may ignore low temperature effects, resulting in unexpected failures with Pb-free materials.
  • Conclusions and Recommendations
    • For applications involving mechanical shock below -40°C, mechanical testing should be performed at or below in-use temperature. Indications are that a problem may exist but further research is required to develop constitutive and failure models so rules of thumb can be established.

7.2.2 Creep Rupture

Creep rupture occurs when a solder joint continues to yield under a sustained load until it can no longer support the load, leading to catastrophic failure. For example, a manifestation of a sustained load can be exerted by wires under tension. CCAs are often subjected to a constant bending load due to fixturing in housing or a shear load if mounted vertically with heavy components. Aging of the solder will affect the creep behavior of the solder, and as a consequence, isothermal aging may strongly reduce the ductility of SAC solders and accelerate creep rupture (Figure 7.5).

Figure 7.5 Creep curve for SAC405 after select isothermal aging conditions [39].
  • Current Baseline Practice
    • Existing design practice aims to eliminate steady-state stresses on solder joints. However, variations in manufacture and assembly can result in the presence of steady-state stresses and the risk of creep rupture.
    • Testing for creep rupture is not normally performed at the CCA level, but it is identified in industry standards such as IPC-SM-785. As with SnPb, the creep behavior of Pb-free solders exhibit primary, secondary, and tertiary zones. The primary zone is more pronounced for Pb-free and may be modeled by a generalized exponential model. The secondary zone may be modeled with a Garofalo Hyperbolic Sine Model. Despite a significant amount of research, failure models for assessing creep rupture in solder interconnects are not readily available.
  • Issues/Gaps/Misconceptions
    • Effects of Sn grain orientation may lead to significant scatter in creep properties [4], an effect that is likely to vary significantly with solder joint size.
    • It is a misconception that mainstream SAC solders always creep less than SnPb solder.
    • Creep is highly dependent upon stress level, temperature, and isothermal aging state.
  • Conclusions and Recommendations
    • For applications involving a sustained load on the interconnect, creep rupture presents a reliability risk. This is particularly true for aged low silver content SAC solders.
    • Do not use SAC solders with less than three weight percent silver in applications where creep rupture may be a failure source.
    • Acceleration factors for creep rupture onset must be established between test and in-use condition over the lifetime of the product.

7.2.3 Electromigration

For SnPb solders, electromigration tends to become significant at direct current densities and above 104 A/cm2, so it is primarily considered a risk for high power flip chip applications. Current practice is to control current densities below 104 A/cm2. The same accelerated test practices and models that were used for SnPb continue to be used for Pb-free.

Accelerated testing suggests that the problem may not be significantly worse with Pb-free solders, and that the legacy models and tests are still applicable. It is common to focus solely on failure by electromigration, ignoring interactions with aging and effects on life under loading conditions such as temperature cycling, vibration, and shock. A redistribution of intermetallic precipitates may have serious consequences regarding material behavior. There is anecdotal evidence that relatively low levels of electromigration can affect the thermal fatigue resistance of Pb-free solders and accelerate Kirkendall voiding in intermetallic bonds to copper pads.

We recommend systematic research to characterize the effect of electromigration on thermal fatigue resistance of Pb-free solders and to develop quantitative models.

In the absence of life time data or validated models, we recommend against use of direct currents above 103 A/cm2 in Pb-free solder joints.

7.2.4 Tin Pest

Metallic tin is susceptible to transformation to a nonmetallic form when exposed to cold temperatures for extended periods of time, leading the tin to crumble into a nonconductive dust. This phenomenon is known as "tin pest." The incorporation of lead into tin is known to suppress this transformation. To date, tin pest has not been shown to occur in Pb-free solder assemblies. This includes temperature cycling conditions with minimum temperature at or below zero. It has been postulated that a rise above the transition temperature (13 °C) may reset the time to conversion, but two years of sub-zero storage of SAC soldered assemblies [40] or four years of low temperature storage [41] did not lead to tin pest either. Still, whether or not actual Pb-free solder joints may be susceptible to it during extended cold service remains unknown [42].

Susceptibility to tin pest may well vary with Pb-free composition, including the presence or absence of particular low-level contaminants picked up during assembly. This significantly complicates the generation and interpretation of tests.

Until such time as the risk can be properly defined, it is recommended that Pb-free solder joints not be used in high reliability A&D assemblies, which will be completely inaccessible for repair and that are anticipated to be continuously exposed to temperatures below 0 °C for extended periods of time (greater than two years).

Barrel Cracks

Copper metallization in PCB plated-through holes is subjected to mechanical damage due to assembly, rework, and repair operations. Further damage can occur under temperature excursions in screening and use. Accumulated mechanical damage can result in loss of electrical continuity due to complete barrel cracking. Such failures are strongly influenced by the quality of the board fabrication process as well as the life cycle loading conditions. Higher Pb-free process temperatures alone will increase damage levels in PTH interconnects. This damage can lead to reduced ability to rework/repair assemblies and result in earlier than expected wearout. Models have been developed to predict barrel cracking [43]. High aspect ratio PTHs present the highest risk [44].

Figure 7.6 Barrel Cracking
  • Current Baseline Practice
    • Interconnect Stress Testing (IST) is widely used for verifying that PCBs can survive multiple reflow operations and provide sufficient service life.
  • Issues/Gaps/Misconceptions
    • Barrel fatigue models have been established for SnPb assemblies. It is unclear if the models need to be updated based on the stress levels that can occur in a Pb-free soldering operation.
    • The ability to repair CCAs may be limited with Pb-free solders due to higher damage sustained under elevated Pb-free soldering operations.
  • Conclusions and Recommendations
    • Increased temperature in assembly and rework can lead to damage of plating in PTHs resulting in elevated infant mortality and early life failures.
    • Current practice of using IST should be applied in qualifying board fabricators. This practice should eliminate early failures. Onset of wearout should be assessed in light of damage associated with the higher Pb-free soldering operations. Before such testing, we recommend pre-conditioning the PCB in multiple Pb-free reflows.
    • Printed wiring boards must be qualified for temperatures encountered in Pb-free assembly process.

Trace Fatigue Cracks

High cycle mechanical loads can lead to trace cracking because of poor adhesion between the copper and laminate, in high stress concentrations where the trace escapes the solder mask, and in cratering of the underlying resin (see Pad Cratering). Trace crack failures have not generally been associated with in-use product failures, but the adoption of Pb-free solders may change this.

  • Current Baseline Practice
    • Trace cracks have not been a major issue with SnPb solder. Material testing may be done periodically by board fabricators and some equipment manufacturers, but it is unclear that sufficient attention has been paid to trace fracture. Test methods for copper ductility and tensile strength are available in IPC-TM-650.
  • Issues/Gaps/Misconceptions
    • The high moduli and propensity for copper dissolution of mainstream Pb-free solders may increase the likelihood of trace cracking, but failures are often conflated with other failure modes induced by mechanical shock and vibration.
    • Models for assessing trace cracking are not readily available. As a result, critical material properties of copper and copper to laminate adhesion have not been identified.
  • Conclusions and Recommendations
    • With the conversion to mainstream SAC solders, trace cracking may result in earlier than expected wearout failures and random failures due to uncontrolled copper dissolution and pad cratering. Control parameters have not been established.
    • Better evaluation methods and guidelines are needed to reduce probability of failure due to trace cracking.

Pad Cratering

Pad cratering is described and illustrated in Section 4.0, Manufacturing.

  • Current Baseline Practice
    • Cratering may be considered a component substrate as well as a PCB defect. Efforts are ongoing to define a new IPC standard for joint level testing to replace CCA testing for cratering under a single overstress or shock. At present, no credible models are available for the prediction or extrapolation of joint or CCA level test results.
  • Issues/Gaps/Misconceptions
    • Trace failure due to cratering competes with solder and intermetallic failures, but it is sensitive to very different factors. Cratering will also influence time to solder or intermetallic failure. This greatly complicates the generalization and extrapolation of CCA level test results to service conditions.
    • A common misconception is that test results can be generalized more than is warranted. Attempts at interpretation rarely distinguish failure under an overstress or shock from wear out under repeated loads (vibration, drops). However, mechanisms and systematic trends are completely different. Notably, repeated loading is much more sensitive to defects. Also, effects of different degradation mechanisms vary with design.
    • Rework reduces the resistance to cratering in subsequent cycling. However, repair is of much greater concern because the preceding aging and humidity exposure further reduces the resistance to the initiation of defects.
  • Conclusions and Recommendations
    • An unavoidable consequence of repair is a significantly reduced resistance to cratering in subsequent vibration or, potentially, even thermal cycling.
    • It is recommended that further systematic studies be performed to support development of a standard for joint level testing of cratering under overstress.
    • A combination of joint level and CCA level testing should be used to qualify rework and repair processes. Evaluation of qualification samples should include cross-sectioning to check for evidence of incipient cratering.

Conductive Anodic Filament Resistance Drops

CAFs are copper corrosion byproducts growing from the anode towards the cathode of a circuit below the surface of a PCB, commonly along separated fiber-epoxy interfaces [44, 45]. Studies by CALCE, University of Toronto, Unovis and NPL have demonstrated that board test specimens subjected to elevated Pb-free process temperatures have a higher propensity to CAF failure.

Standard CAF test procedures for SnPb still apply where specially designed test coupons are required. For board qualification, test procedures must address the impact of Pb-free reflow and wave solder operations as a precondition to any CAF tests. PCB suppliers do not usually test for effects of defects created in assembly or use. Such defects are much more prevalent for Pb-free solders and compatible laminates [46]. A particular concern is defect generation in repair.

Tight conductor spacing, high voltage potentials, and high moisture uptake tend to aggravate increase CAF failures. Introduction of new laminate materials and changes in materials will require strict surveillance of CAF performance.

Creep Corrosion and Dendritic Growth

An important function of the printed wiring board is to provide high surface insulation resistances between adjacent metal conductors of separate electrical circuits. Moisture in the presence of mobile metal ions can result in a loss of surface insulation and ultimately electrical failures. Unlike interconnect failures, surface insulation failure can occur randomly and may be tied to materials selected in design as well as processes used in manufacturing. Corrosion and dendritic induced failures have been held at a relatively low level due to cleaning processes, elimination of active ions in reflow, selection of metal finishes, solder mask materials, and fabrication processes that greatly reduce the risk. Pb-free materials and processes introduce an increased risk for creep corrosion and dendritic failures which occur and evade product validation tests. A clear example is the creep corrosion failures on immersion silver finished CCAs used in computer applications that occurred in sulfur rich environments (Figure 7.6) [47].

Figure 7.7 Comparison of board finishes under sulfur rich environments.
  • Current Baseline Practice
    • To identify surface electrochemical migration issues, board fabricators and CCA manufacturers use tests set forth in IPC-TM-650. These tests include SIR and electrochemical migration. Mixed flowing gas (MFG) tests are also used to examine the propensity for surface corrosion.
  • Issues/Gaps/Misconceptions
    • Despite testing, creep corrosion failures escaped the Pb-free product development process and caused significant financial losses. This indicates a deficiency in existing test methods to help scrutinize products that can potentially fail due to creep corrosion and dendritic growth.
    • New processes and materials can produce unexpected failures that will increase early and useful life failures. Rapid adoption of new processes and material by A&D industry could result in severe consequences. Current qualification test methods have been shown to be insufficient in preventing electrochemical induced failures.
    • Poor wetting of Pb-free solders and higher surface damage, induced by reworking Pb-free assemblies, may result in exposing the copper pads or traces to environments which could lead to electrochemical induced failures.
  • Conclusions and Recommendations
    • New test methods are needed to qualify PCB finishes that prevent electrochemical migration failures.
    • Immersion silver PCB finishes should not be used in A&D products, unless adequate protection against airborne or material induced impurities which promote silver oxidation or chemical corrosion has been provided, and validated by test.

7.2.5 Tin Whisker Shorting

Tin whiskers can grow spontaneously from tin rich surface finishes, reaching lengths ranging from a few microns to several millimeters. Their diameters typically range from less than a micron to about 10 microns, making them very difficult to see even under optical instruments. Whiskers are electrically conductive, presenting risks of electrical shorting and arcing failures. Historically, tin whiskers have been associated with catastrophic system-level failures in A&D hardware [48]. The removal of Pb, a recognized mitigator of tin whiskers, has raised serious concerns over the inclusion of Pb-free parts in A&D systems.

Tin whisker incubation periods can range from days to years, and lengths have been shown to follow a lognormal distribution [49]. As such, it is not clear from statistical assessments, that growth is ever completely arrested. Current industry consensus is [50] that the fundamental mechanisms of whisker growth are too insufficiently understood to predict whisker growth for long periods. Tin whiskers can escape detection during initial screening and testing, only to show up in the field, where there is generally no accepted minimum or maximum time in which tin whisker growth has been declaratively terminated, and can be regarded as innocuous. For most A&D systems, tin whisker induced unreliability will result from randomly distributed failures that manifest themselves as a decreased MTBF at the system-level. Most of these failures will be intermittent, and extremely difficult to properly troubleshoot.

  • Current Baseline Practice
    • The preferred baseline practice is to implement tin whisker risk mitigation plans in accordance with GEIA-STD-0005-2. This document discusses various mitigation activities to be implemented throughout all phases of a program. Details provided in this document and its appendices will not be repeated here.
    • During the design phase, it is necessary to specify mitigation strategies and techniques. This leads to a decision process whereby the adequacy of the mitigations needs to be assessed. Two published models currently employed in the A&D community can be used for this purpose, the so-called “Pinsky model,” and the CALCE "tin whisker risk calculator" [51, 52].
    • Component level testing intended to evaluate whiskering propensity is described in the commercial standard JESD-201. This standard includes in its introduction, a statement to the effect that Pb-free tin should not be used in Class 3 products, which includes A&D.
    • From an A&D equipment manufacturing perspective, three options exist: application of conformal coating, replacement of the tin by SnPb by solder dipping or special plating processes, and reliance on SnPb solder wicking in the assembly process to completely coat Pb-free tin surfaces. Each approach has positive and negatives which need to be considered in the design and manufacturing phases. Qualification of one solder dipping process was provided by a Navy funded project [53]. An industry standard, GEIA-STD-0006 has been issued to cover qualification of these solder dip processes.
  • Issues/Gaps/Misconceptions
    • Conversion to Pb-free electronics systems does not mitigate the tin whisker risk. Fundamental physical models describing tin whisker growth have not been fully developed nor widely accepted. As a result, the available models cannot be used to accurately quantify the risk associated with tin whiskers.
    • Conformal coating provides a high degree of mitigation. However, no coating is perfect and tests indicate that nearly all commonly used coatings can be penetrated by whisker growth. Furthermore, the long-term effectiveness of conformal coating as a whisker mitigator has not been quantified.
    • The diligence required to prevent an unacceptable incorporation of tin adds cost and often results in schedule slippage during manufacture.
    • The tin whisker phenomenon is subject to a number of misconceptions including:
      • Tin whisker failures can only occur in space-based systems (untrue).
      • Tin whisker growth requires the presence of voltage (untrue).
      • Tin whisker growth only occurs in harsh environments (untrue).
      • For a given finish, there is a maximum length beyond which whiskers cannot grow (untrue).
      • If there’s sufficient voltage to fuse a whisker open, failure cannot result (untrue).
  • Conclusions and Recommendations
    • The incorporation of pure tin finishes into A&D systems is a present reality. Present management of tin whisker risks is not optimal, resulting in undefined reliability risks for fielded systems and unnecessary cost and schedule impacts to A&D programs.
    • Tin whisker risks should be managed using GEIA-STD-0005-2.
    • Investigations into currently applied mitigation techniques should be performed with a goal to quantify their efficacy. Development of improved mitigation techniques should then be undertaken, with the goal to developing more effective techniques where necessary.
    • Development of a meaningful test to predict tin whiskering propensity for components should be undertaken.
    • Additional research should be performed to provide greater basic understanding of the tin whiskering phenomenon.

7.2.6 Parts (Not PCB)

Temperature Sensitivity

Mainstream Pb-free solders require process temperatures that can be 20 to 40 °C higher than SnPb solder. While the part supply chain has rapidly converted to Pb-free terminal finishes, many part types still have temperature limits that make them susceptible to damage in a Pb-free assembly process. J-STD-075 has recently been issued to provide a standard for qualifying and identifying temperature sensitive parts.

BGA CTE Warpage

BGA to PCB co-planarity is essential for forming quality interconnects. BGA packages can warp at elevated temperatures, which is exacerbated by the increased Pb-free processing temperatures. JESD-22-B112 has been established as a test to quantify warpage. Warpage issues are normally found in production and may be considered a form of temperature sensitivity.

Figure 7.8 Temperature Process Window, courtesy of IBM Corporation.
  • Recommendations
    • The provisions of J-STD-075 should be employed to manage the effects of temperature sensitive parts on assemblies.
    • The provisions of JESD-22-B112 should be employed to measure BGA warpage. An industry consensus should be arrived at regarding acceptable levels of BGA warpage.
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